1. Field of the Invention
The present invention relates to a pulse extension circuit for extending a pulse signal, and more particularly, to a pulse extension circuit for controlling a pulse extension signal by an initiation signal and a termination signal.
2. Description of the Prior Art
In the prior art, a pulse extension circuit for extending pulse signals utilizes serialized flip-flop circuits for extending the inputted pulse signals. However, if the inputted pulse signal is too short, for instance, if the inputted pulse signal is shorter than a period of a clock signal, the flip-flop circuits cannot sample such short pulse signals according to the clock signal, so that a desired pulse extension signal cannot be generated.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art pulse extension circuit 10. The pulse extension circuit 10 includes D-type flip-flops D1˜Dn and an OR gate 110. Each D-type flip-flop includes a clock input terminal CK, a data input terminal D, an output terminal Q and a reset terminal RB. The D-type flip-flops D1˜Dn are coupled in series, i.e., the data input terminal D of each D-type flip-flop is coupled to the output terminal Q of a previous D-type flip-flop, among which the data input terminal D of the first D-type flip-flop D1 is utilized for receiving a pulse signal IN_PULSE and the output terminal Q of the last D-type flip-flop Dn is directly coupled to the OR gate 110. Moreover, the clock input terminal CK of each D-type flip-flop is utilized for receiving a clock signal CLK. When the clock signal CLK received by the clock input terminal CK is at a descending edge, each of the D-type flip-flops D1˜Dn samples signals of the data input terminal D, and outputs sampling results through the output terminal Q. The reset terminal RB is utilized for receiving a reset signal RS, so as to reset a corresponding D-type flip-flop according to a logic state of the reset signal RS. The OR gate 110 includes input terminals IP1˜IP(n+1) and an output terminal OP. The input terminals IP1˜IP(n+1) are individually coupled to the pulse signal IN_PULSE and the output terminals Q of the D-type flip-flops D1˜Dn are respectively utilized for receiving the pulse signal IN_PULSE and output signals of the D-type flip-flops D1˜Dn; and the output terminal OP is utilized for outputting an OR operation result of the OR gate 110.
Therefore, when the pulse signal IN_PULSE is inputted to the pulse extension circuit 10, each D-type flip-flop is triggered according to the descending edges of the clock signal CLK, samples signals of its own data input terminal D, and outputs the sampling result to the OR gate 110 from the output terminal Q. Please refer to FIG. 2. FIG. 2 is a schematic diagram of signal timing sequences in the pulse extension circuit 10. In FIG. 2, signals TD1˜TDn are respectively corresponding to signals outputted by the output terminals Q of the D-type flip-flops D1˜Dn; a pulse extension signal EXT_PULSE is corresponding to a signal outputted by the output terminal OP of the OR gate 110; and timing points T0, T1, etc. are respectively corresponding to the descending edges of the clock signal CLK. The pulse signal IN_PULSE is inputted to the data input terminal D of the first D-type flip-flop D1 between the timing points T0 and T1. At this time, the first D-type flip-flop D1 is still not triggered by the descending edge of the clock signal CLK, so that the signal TD1 keeps at an initial voltage level, i.e. low logic state. Then, at the timing point T1, the first D-type flip-flop D1 is triggered by the descending edge of the clock signal CLK, and samples the signal of the data input terminal D, so as to transform the voltage level of the signal TD1 from low to high. The pulse signal IN_PULSE terminates between the timing points T2 and T3, and thus at the timing point T3, the sampling result of the data input terminal D of the first D-type flip-flop D1 is at low logic state, so as to transform the voltage level of the signal TD1 from high to low.
In other words, between the timing points T1 and T3, the signal TD1 outputted by the first D-type flip-flop D1 is at high logic state. In like manners, the D-type flip-flops D2˜Dn respectively sample the signals outputted by the previous D-type flip-flops. Therefore, as shown in FIG. 2, the signal outputted by each of the D-type flip-flops delays one period of the clock signal compared with the signal outputted by the previous D-type flip-flop. Eventually, the OR gate 110 performs the OR operation for the pulse signal IN_PULSE and the signals TD1˜TDn. That means, as long as one of the pulse signal IN_PULSE and the signals TD1˜TDn is at high logic state, the pulse extension signal EXT_PULSE outputted by the OR gate 110 will be at high logic state. Thus, the signal duration of the pulse extension signal EXT_PULSE is about n multiples of the period the clock signal CLK, i.e., the number of the D-type flip-flops can determine a desired signal duration extended by the pulse extension circuit 10.
However, when the pulse signal is too short, such as the pulse signal initiating and terminating between the timing points T0 and T1 in FIG. 2, the first D-type flip-flop D1 cannot sample the pulse signal according to the clock signal, so that the pulse extension circuit 10 loses its efficacy. As mentioned above, the prior art pulse extension circuit directly extends the inputted pulse signal, but if the inputted pulse signal is too short, the desired pulse extension signal cannot be generated accordingly.